Links

This page contains links to other projects.

Online Services

• EDA Playground -- Web Interface to many EDA tools, including Yosys
• Blinklight -- A visual FPGA dev tool for simple designs

Free Verilog Simulators

• Icarus Verilog
• Verilator

Free Software for High-Level Circuit Synthesis and/or Analysis

• Chisel -- Constructing Hardware in a Scala Embedded Language
• PandA -- high-level synthesis of C based descriptions
• CLaSH -- A compiler from Haskell to Verilog/VHDL
• MyHDL -- an open source Python package that lets you go from Python to silicon
• Migen -- a Python-based tool that aims at automating further the VLSI design process
• Cx -- A modern C-like language to create digital hardware

Free Software for Low-Level Circuit Synthesis and/or Analysis

• ABC -- extensive tools for synthesis and verification of binary sequential logic
• AIGER -- a format, library and set of utilities for And-Inverter Graphs
• MiniSAT -- the SAT solver library used in Yosys
• Torc -- infrastructure and tool set for mapping, placing, and routing
• RapidSmith -- a research-based, open source FPGA CAD tool for modern Xilinx FPGAs
• Open Circuit Design -- collection of open-source EDA tools, including Qflow
• Coriolis2 -- an ASIC place and route flow
• Workcraft -- a framework for interpreted graph models
• netlistsvg -- SVG schematic from a Yosys JSON netlist
• HAL -- The Hardware Analyzer

Verilog Tutorials

• Learning Verilog with Yosys
• Numato Lab Verilog Tutorial
• ASIC-World Verilog Tutorial
• Nandland: Verilog Examples, Tutorials, and more