InterSynth - Example-Driven Interconnect Synthesis

InterSynth is a command line tool implemented in C++ that generates (synthesizes) interconnects for heterogeneous coarse-grained reconfigurable logic circuits. Its input consists of descriptions of cells (only the interfaces, not the implementations) and example netlists utilizing this cells. These example netlists are then used by InterSynth to generate an interconnect that can implement the given example netlists and other circuits that are similar to these example netlists. This way it is possible to use InterSynth to create interconnects for a domain of applications using examples from this domain to describe it.

InterSynth can generate Verilog HDL files that implement the interconnect and instantiate the cells. It can also generate the configuration bit-streams for implementing netlists on a previously generated interconnect.


Link to the subversion repository: